1. Technical Field
Various embodiments generally relate to an integrated circuit, and more particularly to a self repair device and method for improving repair efficiency during a package repair operation.
2. Related Art
A semiconductor memory such as Dynamic Random Access Memory (hereinafter referred to as “DRAM”) includes a plurality of memory cells arranged in a matrix. Demands for highly integrated semiconductor memory devices are leading to a decrease in the design rule, which defines the minimum feature size of chip lithography. The decrease in the design rule may increase the probability of defects in the semiconductor memory devices, and one or more defects in a chip may cause the chip to be discarded.
The proportion of devices on the wafer found to perform properly is referred to as “yield.” With an increase of defective cells, the yield may decrease. Thus, research is being conducted on methods for efficiently repairing defective cells in order to improve the yield.
Examples of the method for repairing a defective cell may include a technology using a repair circuit which replaces a defective cell with a redundancy cell. In general, the repair circuit includes a redundancy column/row arranged in columns and rows each including a plurality of redundancy memory cells. The repair circuit selects a redundancy column/row in place of a column/row in which a defect occurred.
That is, when a row and/or column address found to be defective is inputted, a redundancy column/row is selected in place of such a defective column/row of a normal memory cell bank.
A semiconductor memory device may include a plurality of fuses to store information as to the address to which the defective cell is assigned. For example, the semiconductor memory device may store the address of the defective cell in the plurality of fuses by selectively cutting them.
Examples of the method for repairing a defective cell in DRAM may include a method for repairing a defective cell at a wafer level and a method for repairing a defective cell at a package level.
The method for repairing a defective cell at the wafer level is to replace a defective cell with a redundancy cell after performing a test at the wafer level. The method for repairing a defective cell at the package level is to replace a defective cell with a redundancy cell at the package level after performing a test at the package level.
In a known self repair mode at the package level, only the redundancy row is used to perform a repair operation, and the redundancy column is not used. Thus, when a column-based defect occurs, the yield may decrease because the column-based defect cannot be repaired.
During a package-level test, a bit failure, a row failure, or a column failure may occur. A semiconductor package having such failure requires a repair circuit, which leads to an increase in the size of each semiconductor chip. Thus, the repair circuit may cause a decrease in the net die per wafer.
If a semiconductor memory device has only a repair circuit for a row self repair mode used in the semiconductor package, such a self repair can be performed only in the row redundancy. Thus, a bit failure and a row failure can be repaired, but a column failure cannot be repaired.
Furthermore, in order to increase the yield, test process must be repeated several times. When such a situation is repeated, the yield ramp-up time may be increased.